High Performance Activity Migration for Thermally Constrained Single Chip Multi-Cores Duration: 12/31/2006 - 12/31/2008 Funded by: Cyprus Research Promotion Foundation (RPF) Amount: 43240 CYP Members: Yiannakis Sazeides and He Liqiang : Department of Computer Science, University of Cyprus, Nicosia, Cyprus Pierre Michaud and Andre Seznec : IRISA/INRIA, Rennes, France Introduction During the last decade we have been witnessing an ever growing demand for high performance but simple to design computing devices. This demand is created by two conflicting trends and presents a formidable challenge for the computing industry: (1) the computing market is characterized by an unprecedented diversity of computationally and memory intensive applications calling for high performance cores, (2) and at the same time the need for low cost, low power and time-to-market constraints have never been stringent. This tension has created an impetus for high performance but complexity-effective computer designs. One of the industry's responses, to the rising need for performance but with manageable design complexity, is single chip multi-core processors. A two way general purpose multi-core is already a reality and with increasing on-chip capacity many more cores will soon be available on a single chip. Multi-cores offer the means to increase performance with thread and program level parallelism. Also, their regular organization leads naturally to lower design complexity. However, the parallel execution on many cores in a single chip can result in high power consumption and power-density (temperature) which may necessary to operate cores at a lower voltage and frequency to ensure efficient and/or correct operation. Activity-migration is an emerging method for research that leverages multi-cores to address power design complexities. For instance, activity-migration can improve power efficiency by transferring the execution of a thread to a core that better matches its power needs and can help alleviate the power density (temperature) problem by distributing power consumption more uniformly over the entire chip. This research project aims to establish, with the use of power, temperature and performance simulators, how effective is thread activity-migration at solving the power density problem for a thermally constrained multi-core and determine how to best implement activity-migration in a multi-core.

Publications Initial Results on the Performance Implications of Thread Migration on a Chip Multi-Core - Y. Sazeides, P. Michaud, L. He, D. Fetis, C. Ioannou, P. Charalambous and A. Seznec 3rd HiPEAC Industrial Workshop, Haifa, Israel (April 2007) Talk